1. Field of the Invention
The present invention relates generally to a semiconductor wafer polishing device and a polishing method thereof. More particularly, the invention relates to a polishing method of an interlayer insulation layer in a fabrication process of a semiconductor device.
2. Description of the Related Art
In general, when an interlayer insulation layer is deposited on an active element, such as metal oxide semiconductor (MOS) transistor or so forth, or a Al wiring after patterning thereof, uneven pattern similar to patterns of the active element, Al wiring or so forth should appear on a surface of the interlayer insulation layer. Such uneven pattern on the surface of the semiconductor can affect for precision of machining dimension in a formation process of an upper layer wiring in the semiconductor, particularly in lithographic process.
On the other hand, in the recent years, increasing of density of wiring pitch or development of multilayer wiring, it has been inherent to planarize the semiconductor substrate. For example, it has been becoming difficult to satisfy a demanded level of flatness of the surface of the interlayer insulation layer as required in the semiconductor device fabrication process by the conventional method for planarizing recessed portion of the surface of the interlayer insulation layer by fluidized coat layer, such as spion glass or the like.
Therefore, a chemical mechanical polishing (CMP) performing planarization of the surface of the interlayer insulation layer by polishing chemical mechanically is currently used.
While the chemical mechanical polishing method has higher performance than the conventional planarization method in terms of ability of planarization, the chemical mechanical polishing method is slightly low in controllability. Primary reason why the chemical mechanical polishing has lower controllability, is huge deposition amount or polishing amount.
For example, when a shape having a step (wiring) of 1 .mu.m is planarized by the chemical mechanical polishing method with leaving an insulation layer in a thickness of 1 .mu.m on the wiring, the insulation layer is deposited on the wiring in a thickness of 2.5 to 3 .mu.m and then the insulation layer on the wiring is removed by chemical mechanical polishing method in the extent of 1.5 to 2 .mu.m. For leaving the insulation layer in a thickness of 1 .mu.m on the wiring, process steps of deposition in a thickness of 3 .mu.m and thereafter polishing in a thickness of 2 .mu.m have to be performed. Accordingly, influence of deposition and influence of polishing are caused in combination. Assuming that a fluctuation range in respective process steps of deposition and polishing is 10 percents, a fluctuation in the extent of 0.5 .mu.m is caused.
On the other hand, as a reason why fluctuation factor is significant in the chemical mechanical polishing method, an abrasion pad used in the chemical mechanical polishing method is constantly subject secular change, difference of the individual polishing pad is significant, and degradation of the polishing pads can be different depending upon pattern layout on the surface of the semiconductor wafer. The significant fluctuation makes control difficult.
FIG. 8 is a longitudinal section of a basic construction of the conventional polishing device. On an upper surface of a platen 1 as a rotary body, an abrasive pad 11 is attached. Above the platen 1, a carrier 3 for holding the semiconductor wafer 15 under pressure is provided. Since the carrier 3 is directly connected to the spindle mechanism 14, it can be driven for rotation.
Accordingly, polishing is performed by setting the semiconductor wafer 15 on the carrier 3 orienting a surface to be polished by the semiconductor wafer 15 toward the abrasive pad 11. Then, the carrier 3 is lowered onto the platen 1 in rotation to apply a load to perform polishing by driving the carrier 3 to rotate in the same direction as that of the platen 1 with supplying an abrasive on the abrasive pad 11 from a nozzle 13. In practical polishing device, such basic units are constructed in various layout.
Particular example of the polishing device is shown in FIGS. 9 to 11. The polishing device shown in FIG. 9 is constructed with the platen 1, the carrier 3, a washing platen 16, a head block 2, a loader portion 6, an unloader portion 7, a loader portion 4 and a layer thickness measuring mechanism 5. One carrier 3 is provided for one platen 1 for polishing and one platen 16 for washing. This device has most basic construction.
The polishing device shown in FIG. 10 is constructed with the platen 1, the carrier 3, the head block 2, the loader 6, the unloader 7, a load cup 4, the layer thickness measuring mechanism 5, a shaft 17, and a handling arm 18. Two carriers 3a and 3b are provided for one platen 1 for polishing to slightly improve production ability.
The polishing device shown in FIG. 11 is constructed with platens 1d to 1f, the carriers 3a to 3d, the head block 2 and the load cup 4(4a). For three platens 1d to 1f for polishing, four carriers 3a to 3d are arranged with equal angular interval of 90 degrees. In this case, one semiconductor wafer can be dividingly polished between the polishing platens 1d to 1f. Also, three semiconductor wafers can be processed simultaneously in parallel to improve production ability.
Including the devices set forth above, there are various constructions of polishing devices having one or two carriers 3 for each of a plurality of platens 1 and dividing between a plurality of platens 1 by stepwise motion of the carrier 3. These polishing devices have constructions modified from the basic construction having one carrier for one platen for improving throughput.
There is unstable factor in chemical mechanical polishing method as set forth above. for example, instability occurs by the polishing device using the layer thickness measuring mechanism 5 which located in a region outside of a polishing portion of the unloader portion as a measure therefor. As such polishing devices, the devices shown in FIGS. 9 and 10 are present.
After polishing, remaining layer thickness is measured after completion of polishing by the layer thickness measuring mechanism 5 arranged in the vicinity of the unloader 7 to stop polishing when the remaining layer thickness is out of a predetermined standard range. In the alternative, if the remaining layer thickness is out of a predetermined standard range, an offset from the predetermined polishing amount is calculated from an actually measured value to reflect in a polishing period of the semiconductor wafer after measurement.
In the conventional polishing device set forth above, there is a low probability that the first pilot wafer will fall within the standard, oxide layer thickness of the semiconductor wafers without polishing measuring all wafers, followed by feedback in connection with secular change of polishing rate the feedback has a delay of one or two runs resulting in difficulty in achieving high control the oxide layer thickness after polishing.
On the other hand, when measurement for all of polished semiconductor wafer is performed with the construction improving throughput as multi-head or multi-table, a problem is encountered in that the throughput is determined by the layer thickness measuring mechanism. Accordingly, measurement of only part of the semiconductor wafer can be performed per each run.
In the nature, it is ideal to measure the residual layer thickness of the insulation layer on the semiconductor wafer within the device. However, in particularly the semiconductor wafer with pattern, it is not possible to perform polishing with measuring the residual layer thickness. Accordingly, it has been desired to achieve both of improvement of controllability of the residual layer and production ability.